CKO_DELAY=ADV3, S_CYCLES=STEP_NUM64, PCM_CH_SET=DISABLED
Mode control
| PCM_CH_SET | Specifies PCM output channels as mono or stereo: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET) 0 (DISABLED): Channel disabled 1 (MONO_L): Mono left channel enable 2 (MONO_R): Mono right channel enable 3 (STEREO): Stereo channel enable |
| SWAP_LR | Input data L/R channel swap: ‘1’: Right/Left channel recording swap ‘0’: No Swap (Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP) |
| S_CYCLES | Set time step for gain change during PGA or soft mute operation in number of 1/a sampling rate. (Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES) 0 (STEP_NUM64): 64steps 1 (STEP_NUM96): 96steps 2 (STEP_NUM128): 128steps 3 (STEP_NUM160): 160steps 4 (STEP_NUM192): 192steps 5 (STEP_NUM256): 256steps 6 (STEP_NUM384): 384steps 7 (STEP_NUM512): 512steps |
| CKO_DELAY | Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY) 0 (ADV3): CLK_IS is 3*PDM_CLK period early 1 (ADV2): CLK_IS is 2*PDM_CLK period early 2 (ADV1): CLK_IS is 1*PDM_CLK period early 3 (NO_DELAY): CLK_IS is the same as PDM_CKO 4 (DLY1): CLK_IS is 1*PDM_CLK period late 5 (DLY2): CLK_IS is 2*PDM_CLK period late 6 (DLY3): CLK_IS is 3*PDM_CLK period late 7 (DLY4): CLK_IS is 4*PDM_CLK period late |
| HPF_GAIN | Adjust high pass filter coefficients. H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ] (Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN) |
| HPF_EN_N | Enable high pass filter (active low) ‘1’: Disabled. ‘0’: Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD) |